Curated demo index // synchronized

Your next silicon
tapes out here.

A precise job signal for the engineers designing the systems beneath every intelligent machine.

QUERY BUS READY // 08 matched signalsTIP: Select a pin to route by domain

GLOBAL

VC

CAREER / DIE

PROCESS: 03nm / OPEN
STATUS: LIVE

Open roles

8curated demo index

Companies

8active teams

Candidate demand

129interest signals

Signal router

Choose an engineering pin.

Route the role index by discipline. Each pin is tuned to a critical silicon function.

Role index // all functions

Datasheet listings

no filters
Job / functionProtocol / toolsExperienceLocationCompensationSignal
UVMSystemVerilogPCIe 6.0
5–8 years

Austin, TX

Hybrid · 3 days on-site

$168k–$214k

BAND A

VerilogCoherencyNoC
4–7 years

Santa Clara, CA

On-site · Core silicon team

$175k–$225k

BAND A

InnovusSTA3nm
8–11 years

Boston, MA

Hybrid · 2 days on-site

$190k–$246k

BAND A

ATPGMBISTISO 26262
3–6 years

Detroit, MI

Hybrid · Flex schedule

$142k–$187k

BAND B

SerDesPLLFinFET
5–9 years

Irvine, CA

On-site · Lab access

$171k–$230k

BAND A

RISC-VPerf ModelOoO
7–12 years

Remote · US

Remote · Quarterly offsite

$185k–$245k

BAND A

FlowPythonTcl
4–8 years

Raleigh, NC

Hybrid · 2 days on-site

$151k–$202k

BAND B

YieldHeterogeneousATE
4–7 years

Phoenix, AZ

On-site · Factory & lab

$137k–$181k

BAND B

Showing 8 of 8 curated componentsCandidate demand weighted by domain signal

VLSICareer // Global VLSI Network

Precision recruiting signal for the teams building silicon.

VERIFICATIONIMPLEMENTATIONARCHITECTUREPRODUCTIZATION
Built with GenMB
Built with GenMB